Design of Optoelectronic Chip Packaging and Integration Method Based on SiP Technology

Author:

Xuan Hui1,Xiaoyong Miao2,Guohua Gao1

Affiliation:

1. Tongfu Microelectronics Co. Ltd.,Nantong,China

2. Fudan University,School of Microelectronics,Shanghai,China

Publisher

IEEE

Reference25 articles.

1. Influence of copper pillar bump structure on flip chip packaging during reflow soldering: a numerical approach[J];Hafiz;Microelectronics international: Journal of ISHM--Europe, the Microelectronics Society--Europe

2. The Influence of Epoxy Molding Compound Poissons Ratio on the Reliability of Ball Grid Array Packaging[J];Chenglong;Journal of Integration Technology,2021

3. Design, integration and implementation of crypto cores in an SoC environment

4. Thermal Cycling Test and Simulation of Fan-Out Chip-Last Panel-Level Packaging for Heterogeneous Integration

5. Sensitivity Analysis for Geometrical Parameters of BGA in Flip-Chip Packaging Under Random Shear Stress and Thermal Temperature

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