Author:
Lacy W.S.,Cruz-Rivera J.L.,Wills D.S.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Signal Processing
Cited by
7 articles.
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1. Sparse 3-D NoCs with Inductive Coupling;Proceedings of the 56th Annual Design Automation Conference 2019;2019-06-02
2. 3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface;2017 14th International Symposium on Pervasive Systems, Algorithms and Networks & 2017 11th International Conference on Frontier of Computer Science and Technology & 2017 Third International Symposium of Creative Computing (ISPAN-FCST-ISCC);2017-06
3. Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface;IEICE Transactions on Information and Systems;2016
4. Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips;2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip;2015-09
5. An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2008-02-01