Design and Implementation of High Frequency Functional Signal Generator using DDFS based on 16-stage pipelined CORDIC architecture-Reference-Cited by-同舟云学术

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Design and Implementation of High Frequency Functional Signal Generator using DDFS based on 16-stage pipelined CORDIC architecture

Published:2022-05-27 Issue: Volume: Page:
ISSN:
Container-title:2022 3rd International Conference for Emerging Technology (INCET)
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Author:

Mohanty Kalinga¹,Reddy D. Ramesh¹,P Chitra²,G Ramana Reddy³,Sankar P. Ravi¹,Prakash K.¹

Affiliation:

1. National Institute of Technology, Warangal,Department of Electronics & Communication Enginnering,Warangal,India,506004

2. SIST - (Deemed to be University),Department of ECE,Chennai,Tamilnadu,India

3. SIST (Deemed to be University),Department of ECE,Chennai,Tamilnadu,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9823393/9823966/09825431.pdf?arnumber=9825431

Reference15 articles.

1. Sine and cosine generator using CORDIC algorithm implemented in ASIC

2. FPGA Implementation of Pipelined CORDIC Sine Cosine Digital Wave Generator

3. Study and Implementation of Ultrasonic Generator Based on FPGA

4. FPGA implementation and power efficient CORDIC based ADPLL for signal processing and application

5. DIRECT DIGITAL SYNTHESIS OF SIGNALS IN RADIOLOCATION, COMMUNICATION AND TELECOMMUNICATION SYSTEMS

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Pipelined CORDIC Architecture Based DDFS Design and Implementation;2023 IEEE 20th India Council International Conference (INDICON);2023-12-14

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