LLC Block Reuse Predictor Design using Deep Learning to Mitigate Soft Error in Multicore
Author:
Affiliation:
1. New Alipore College,Dept. of Computer Sc.,Kolkata,WB,India
2. Sammilani Mahavidyalaya,Dept. of Computer Sc.,Kolkata,WB,India
3. IIT Delhi,Dept. of CSE,Delhi,India
4. IIEST Shibpur,Dept. of CST,Shibpur,WB,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10483275/10483296/10483490.pdf?arnumber=10483490
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1. Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations
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3. Lowering Minimum Supply Voltage for Power-Efficient Cache Design by Exploiting Data Redundancy
4. RAW-Tag: Replicating in Altered Cache Ways for Correcting Multiple-Bit Errors in Tag Array
5. CLEAR: Cache Lines Error Accumulation Reduction by exploiting invisible accesses
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