An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs
Author:
Funder
National Science Foundation
Microchip Technology Inc
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
https://ieeexplore.ieee.org/ielam/4/9694622/9485113-aam.pdf
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Current-Steering DAC Architecture Design for Amplitude Mismatch Error Minimization;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. A 14-bit 6GS/s DAC Achieving >65dBc SFDR with Bilateral Output Impedance Compensation in 22nm CMOS;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. Design of Low Power Current Steering DAC Using 45nm CMOS Technology;2024 Third International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE);2024-04-26
4. Mismatch error compensation of hybrid CS‐DAC to achieve high figure of merit utilizing on‐chip self‐healing assisted swap‐enabled randomization technique;International Journal of Circuit Theory and Applications;2023-11-30
5. Adaptive Cancellation of Inter-Symbol Interference in High-Speed Continuous-Time DACs;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-11
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