A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver-Reference-Cited by-同舟云学术

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A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver

Published:2022-01 Issue:1 Volume:57 Page:32-43
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Bailey James^ORCID,Shakiba Hossein^ORCID,Nir Ehud^ORCID,Marderfeld Grigory,Krotnev Peter^ORCID,LaCroix Marc-Andre^ORCID,Cassan David,Tonietto Davide^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9664397/09535163.pdf?arnumber=9535163

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A High Efficiency 14–28 Gb/s Tunable Receiver Analog Front-End in 65 nm CMOS Technology;Journal of Circuits, Systems and Computers;2023-10-28

2. Equalization technology and Quantization analysis for Data-converter Based PAM4 SerDes Link;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

3. Precursor ISI Cancellation Sliding-Block DFE for High-Speed Wireline Receivers;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-10

4. A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes;IEEE Journal of Solid-State Circuits;2023-03

5. MMSE Equalizer Design Optimization for Wireline SerDes Applications;IEEE Transactions on Circuits and Systems I: Regular Papers;2023

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