A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver-Reference-Cited by-同舟云学术

A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver

Published:2022-01 Issue:1 Volume:57 Page:32-43
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Bailey James^ORCID,Shakiba Hossein^ORCID,Nir Ehud^ORCID,Marderfeld Grigory,Krotnev Peter^ORCID,LaCroix Marc-Andre^ORCID,Cassan David,Tonietto Davide^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9664397/09535163.pdf?arnumber=9535163

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