Sparse Hamming Graph: A Customizable Network-on-Chip Topology-Reference-Cited by-同舟云学术

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Sparse Hamming Graph: A Customizable Network-on-Chip Topology

Published:2023-07-09 Issue: Volume: Page:
ISSN:
Container-title:2023 60th ACM/IEEE Design Automation Conference (DAC)
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Author:

Iff Patrick¹,Besta Maciej¹,Cavalcante Matheus²,Fischer Tim²,Benini Luca²,Hoefler Torsten¹

Affiliation:

1. ETH Zurich,Department of Computer Science,Zurich,Switzerland

2. ETH Zurich,Department of Information Technology and Electrical Engineering,Zurich,Switzerland

Funder

European Research Council

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10247654/10247655/10247754.pdf?arnumber=10247754

Reference24 articles.

1. Flattened Butterfly Topology for On-Chip Networks

2. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

3. PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

4. Wire routing in NP-complete;kramer,1982

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

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