Hybrid Obfuscation of Chiplet-Based Systems
Author:
Affiliation:
1. McGill University,THInK Team,ECE Department,Montreal,Canada
2. University of California,SsysArch Lab,ECE Department,Los Angeles,CA,USA
3. University of California,CHIPS,ECE Department,Los Angeles,CA,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10247654/10247655/10247738.pdf?arnumber=10247738
Reference13 articles.
1. Power Delivery for Silicon Interconnect Fabric
2. Wafer‐Scale Integration
3. Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems
4. Designing a 2048-Chiplet, 14336-Core Waferscale Processor
5. Efficient and secure split manufacturing via obfuscated built-in self-authentication
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1. SCRIPT: A Multi-Objective Routing Framework for Securing Chiplet Systems against Distributed DoS Attacks;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12
2. Hybrid Interconnect Infrastructure for Inter-Chiplet Communication in Wafer-Scale Systems;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28
3. DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer;IET Information Security;2024-04-12
4. Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
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