In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time
Author:
Affiliation:
1. Pohang University of Science and Technology,Pohang,Korea
2. Seoul National University,Seoul,Korea
Funder
IC Design Education Center
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10247654/10247655/10247975.pdf?arnumber=10247975
Reference10 articles.
1. A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks
2. A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor
3. A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks
4. Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs
5. PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference
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1. Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism;Journal of Low Power Electronics and Applications;2024-01-04
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