DVINO: A RISC-V Vector Processor Implemented in 65nm Technology-Reference-Cited by-同舟云学术

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology

Published:2022-11-16 Issue: Volume: Page:
ISSN:
Container-title:2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)
language:
Short-container-title:

Author:

Cabo Guillem¹,Candon Gerard¹,Carril Xavier¹,Doblas Max¹,Dominguez Marc¹,Gonzalez Alberto¹,Hernandez Cesar²,Jimenez Victor¹,Kostalampros Vatistas¹,Langarita Ruben¹,Leyva Neiel²,Lopez-Paradis Guillem¹,Mendoza Jonnatan¹,Minervini Francesco¹,Pavon Julian¹,Ramirez Cristobal¹,Rodas Narcis¹,Reggiani Enrico¹,Rodriguez Mario¹,Rojas Carlos¹,Ruiz Abraham¹,Soria Victor¹,Suanes Alejandro³,Vargas Ivan¹,Figueras Roger¹,Fontova Pau¹,Marimon Joan¹,Montabes Victor¹,Cristal Adrian¹,Hernandez Carles¹,Martinez Ricardo³,Moreto Miquel¹,Moll Francesc¹,Palomar Oscar¹,Ramirez Marco A.²,Rubio Antonio⁴,Sacristan Jordi³,Serra-Graells Francesc³,Sonmez Nehir¹,Teres Lluis³,Unsal Osman¹,Valero Mateo¹,Villa Luis²

Affiliation:

1. Barcelona Supercomputing Center (BSC),Barcelona,Spain

2. Centro de Investigación en Computación, Instituto Politécnico Nacional (CIC-IPN),Mexico City,Mexico

3. Institut de Microelectrònica de Barcelona, IMB-CNM (CSIC),Spain

4. Universitat Politècnica de Catalunya (UPC),Barcelona,Spain

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9969904/9970010/09970128.pdf?arnumber=9970128

Reference18 articles.

1. Untethered lowRISC v0.2;lowRISC·lowRISC,0

2. A Low-Overhead Coher- ence Solution for Multiprocessors with Private Cache Memories;papamarcos;Proceedings of the 11th annual international symposium on Computer architecture - ISCA '84,0

3. Overview of the debug infrastructure;lowRISC·lowRISC,2018

4. The Open SoC Debug Documentation Library;The Open SoC Debug Contributors,2018

5. The Generic Logic Interfacing Project;Institute for Integrated Systems (LIS),2018

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology;2023 38th Conference on Design of Circuits and Integrated Systems (DCIS);2023-11-15

2. OpenPiton Optimizations Towards High Performance Manycores;Proceedings of the 16th International Workshop on Network on Chip Architectures;2023-10-28

3. Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-10