A Wideband 4-Phase Phase-Locked Loop for Single-Slope Ramp ADC in SCA ASIC-Reference-Cited by-同舟云学术

A Wideband 4-Phase Phase-Locked Loop for Single-Slope Ramp ADC in SCA ASIC

Published:2023-06 Issue:6 Volume:70 Page:1015-1022
ISSN:0018-9499
Container-title:IEEE Transactions on Nuclear Science
language:
Short-container-title:IEEE Trans. Nucl. Sci.

Author:

Wang Yuting¹^ORCID,Zhao Lei¹^ORCID,Qin Jiajun¹^ORCID,Guo Jiacheng¹,Li Li¹,Liu Shubin¹^ORCID,An Qi¹

Affiliation:

1. State Key Laboratory of Particle Detection and Electronics and the Department of Modern Physics, University of Science and Technology of China, Hefei, China

Funder

National Natural Science Foundation of China

Youth Innovation Promotion Association CAS

CAS Center for Excellence in Particle Physics

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Nuclear Energy and Engineering,Nuclear and High Energy Physics

Link

http://xplorestaging.ieee.org/ielx7/23/10154183/10015863.pdf?arnumber=10015863

Reference22 articles.

1. CMOS 1.6 GHz Bandwidth 12 Bit Time Interleaved Pipelined ADC

2. Single Event Effects Testing for the ADC12DJ3200QML-SP 12-bit, Dual 3.2-GSPS Single 6.4-GSPS, RF-Sampling, JESD204B, Analog-to-Digital Converter (ADC)

3. Design and performance of the 6 GHz waveform digitizing chip DRS4

4. The SAMPIC Waveform and Time to Digital Converter

5. Improved switched capacitor cell for a 3 GHz 20 GS/s waveform digitizing ASIC

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