System Level IR Drop Impact on Chip Power Performance Signoff for RISC-V System on Chip-Reference-Cited by-同舟云学术

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System Level IR Drop Impact on Chip Power Performance Signoff for RISC-V System on Chip

Published:2022-10-26 Issue: Volume: Page:
ISSN:
Container-title:2022 17th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)
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Author:

Yong Kin Fei¹,Lim Chin Theng¹,Teng Wei Khoon¹

Affiliation:

1. Physical Design Technology Group, StarFive Technology International, Unit 1.22-1.26, GBS@Mayang, Jalan Mayang Pasir 1, Bayan Baru, 11950, Bayan Lepas,Penang

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9966654/9966628/09966707.pdf?arnumber=9966707

Reference7 articles.

1. Power Integrity Analysis of Low Power SOC Design

2. Dynamic voltage (IR) drop analysis and design closure: Issues and challenges

3. Signal and Power Integrity – Simplified;bogatin;Prentice Hall,2004

4. System power distribution network theory and performance with various noise current stimuli including impacts on chip level timing

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. OhmNet: General Static IR Drop Estimation Neural Network Architecture;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

2. Analysis of IR Drop for Robust Power Grid of Semiconductor Chip Design: A Review;ITM Web of Conferences;2023

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