A 0.99μs FFT-Based Fast-Locking, 0.82GHz-to-4.1GHz DPLL-Based Input-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces
Author:
Affiliation:
1. Seoul National University,Seoul,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10121189/10121178/10121322.pdf?arnumber=10121322
Reference5 articles.
1. A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range
2. Analysis of a 28-nm CMOS Fast-Lock BangBang Digital PLL with 220-fs RMS Jitter for Millimeter-Wave Communication;tsai;JSSC,2020
3. 17.2 A 66fsrmsJitter 12.8-to-15.2 GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking;santiccioli;ISSCC,2020
4. A 18.6-to-40.1 GHz 201.7dBc/Hz FoMT Multi-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting;shu;ISSCC,2020
5. An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator
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