A Review on the Effects of Technology on CMOS and CPL Logic Style on Performance, Speed and Power Dissipation-Reference-Cited by-同舟云学术

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A Review on the Effects of Technology on CMOS and CPL Logic Style on Performance, Speed and Power Dissipation

Published:2018-11 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE Electron Devices Kolkata Conference (EDKCON)
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Author:

Hussain Inamul,Singh Avtar,Chaudhury Saurabh

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8765317/8770219/08770506.pdf?arnumber=8770506

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Simulation and Characterization of Carbon Nanotube-based 2:1 Multiplexer Electrical Properties;Journal of Physics: Conference Series;2023-10-01

2. Review of Performance Analysis of Some Basic Full Adder Circuits;2023 International Conference on Advanced & Global Engineering Challenges (AGEC);2023-06-23

3. Performance Analysis of Carbon Nanotube Transistors - A Review;2022 6th International Conference on Trends in Electronics and Informatics (ICOEI);2022-04-28

4. Tetra-variate scrutiny of diverse multiplexer techniques for designing a barrel shifter for low power digital circuits;Microprocessors and Microsystems;2022-04

5. The impact of decision-making styles (effectuation logic and causation logic) on firm performance: a meta-analysis;Journal of Business & Industrial Marketing;2022-03-21

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