A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells-Reference-Cited by-同舟云学术

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A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells

Published:2019-05 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Moreau Ludovic,Dekimpe Remi,Bol David

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8682239/8702066/08702680.pdf?arnumber=8702680

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Current Crafting: Mastering Low-Power Configuration Methods;2023 International Conference on Next Generation Electronics (NEleX);2023-12-14

2. Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design;Sensors;2022-07-29

3. A low quiescent current power-on-reset circuit with configurable trip voltage;AEU - International Journal of Electronics and Communications;2022-05

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