Author:
Wang Yanfeng,Zhou Qiang,Hong Xianlong,Cai Yici
Cited by
10 articles.
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1. Clock Aware Low Power Placement;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
2. Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018-01
3. Clock-Tree-Aware Incremental Timing-Driven Placement;ACM Transactions on Design Automation of Electronic Systems;2016-07-26
4. Progress and Challenges in VLSI Placement Research;Proceedings of the IEEE;2015-11
5. Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2015-04