Architecture Generator for Type-3 Unum Posit Adder/Subtractor
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8334884/8350884/08351142.pdf?arnumber=8351142
Cited by 20 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Review of Posit Arithmetic for Energy-Efficient Computation: Methodologies, Applications, and Challenges;Design and Applications of Emerging Computer Systems;2023-08-17
2. PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
3. Hardware Implementation of Posit Numeration System using FPGA for Signal Processing Applications;2023 7th International Conference on Trends in Electronics and Informatics (ICOEI);2023-04-11
4. Design of Risc-V Processing Unit Using Posit Number System;2023 4th International Conference on Signal Processing and Communication (ICSPC);2023-03-23
5. CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism;Journal of Systems Architecture;2023-02
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