FPGA design of a coordinate descent data detector for large-scale MU-MIMO-Reference-Cited by-同舟云学术

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FPGA design of a coordinate descent data detector for large-scale MU-MIMO

Published:2016-05 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Wu Michael,Dick Chris,Cavallaro Joseph R.,Studer Christoph

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7515073/7527154/07538942.pdf?arnumber=7538942

Cited by 29 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel Low-Complexity Massive MIMO Detector with Near-Optimum Performance;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. High-Throughput Accelerator for Exact-MMSE Soft-Output Detection in Open RAN Systems;IEEE Access;2024

3. A Low-Complexity Soft-Output Massive MIMO Detector With Near-Optimum Performance;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

4. Improved Two-Dimensional Double Successive Projection Algorithm for Massive MIMO Detection;International Journal of Electronics and Telecommunications;2023-07-26

5. Hint: a Clue as to Where to Start an Iterative Massive MIMO Detection Process;ICC 2023 - IEEE International Conference on Communications;2023-05-28

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