A bit-serial approximate min-sum LDPC decoder and FPGA implementation

Author:

Darabiha A.,Carusone A.C.,Kschischang F.R.

Publisher

IEEE

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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3. GC-Like LDPC Code Construction and its NN-Aided Decoder Implementation;IEEE Open Journal of Circuits and Systems;2024

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5. A Second Minimum Approximation Method for Layered Min-Sum Decoding of QC-LDPC Codes;2023 4th Information Communication Technologies Conference (ICTC);2023-05-17

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