Introducing deglitched-feedback plus convergent encoding for straight hardware implementation of asynchronous finite state machines
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7152138/7168553/07169154.pdf?arnumber=7169154
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Balanced State Splitting of Finite State Machines for FPGA Implementations of Control Units;Lecture Notes in Computer Science;2024
2. Design of Locally-Clocked Asynchronous Finite State Machines with no Memory Elements;2023 IEEE Seventh Ecuador Technical Chapters Meeting (ECTM);2023-10-10
3. Balanced Power, Speed and Area Transformation Procedure for Finite State Machines;2022 IEEE International Conference on Systems, Man, and Cybernetics (SMC);2022-10-09
4. State Merging and Splitting Strategies for Finite State Machines Implemented in FPGA;Applied Sciences;2022-08-14
5. Combined State Splitting and Merging for Implementation of Fast Finite State Machines in FPGA;Computer Information Systems and Industrial Management;2020
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