A high-voltage DC bias architecture implementation in a 17 Gbps low-power common-cathode VCSEL driver in 80 nm CMOS-Reference-Cited by-同舟云学术

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A high-voltage DC bias architecture implementation in a 17 Gbps low-power common-cathode VCSEL driver in 80 nm CMOS

Published:2015-05 Issue: Volume: Page:
ISSN:
Container-title:2015 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Szilagyi Laszlo,Belfiore Guido,Henker Ronny,Ellinger Frank

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7152138/7168553/07169164.pdf?arnumber=7169164

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. 910 nm Single-Mode VCSELs and its Application for Few-Mode Transmission over Graded-Index Single-Mode Fibers;2020 22nd International Conference on Transparent Optical Networks (ICTON);2020-07

3. Energy-Efficient 50+ Gb/s VCSELs for 200+ Gb/s Optical Interconnects;IEEE Journal of Selected Topics in Quantum Electronics;2019-11

4. Survey of Photonic and Plasmonic Interconnect Technologies for Intra-Datacenter and High-Performance Computing Communications;IEEE Communications Surveys & Tutorials;2018

5. 25-Gbps 3-mW/Gbps/ch VCSEL Driver Circuit in 65-nm CMOS for Multichannel Optical Transmitter;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2018

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