1. Robust CNFET Circuit Sizing Optimization;2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT);2022-04-18
2. LDE-aware Analog Layout Migration with OPC-inclusive Routing;ACM Transactions on Design Automation of Electronic Systems;2020-10-12
3. AZUPT: Adaptive Zero Velocity Update Based on Neural Networks for Pedestrian Tracking;2019 IEEE Global Communications Conference (GLOBECOM);2019-12
4. Analog Layout Retargeting With Process-Variation-Aware Hybrid OPC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-03
5. Process-Variation-Aware Rule-Based Optical Proximity Correction for Analog Layout Migration;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017-08