Author:
Hosaka Takahiro,Hoang Trong-Thuc,Hoang Van-Phuc,Le Duc-Hung,Inoue Katsumi,Pham Cong-Kha
Cited by
1 articles.
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1. A hardware acceleration architecture design for histogram equalization with locking features;2023 IEEE International Conference on Sensors, Electronics and Computer Engineering (ICSECE);2023-08-18