High-speed Sparse Ising Model on FPGA
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8882388/8884793/08885105.pdf?arnumber=8885105
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Ising Machines Using Parallel Spin Updating Algorithms for Solving Traveling Salesman Problems;Design and Applications of Emerging Computer Systems;2023-08-17
2. Efficient Traveling Salesman Problem Solvers using the Ising Model with Simulated Bifurcation;2022 Design, Automation & Test in Europe Conference & Exhibition (DATE);2022-03-14
3. Implemented Parallel Annealing in Scalable Fully Coupled Annealing Processing System;2022 IEEE 20th Jubilee World Symposium on Applied Machine Intelligence and Informatics (SAMI);2022-03-02
4. Annealing Processing Architecture of 28-nm CMOS Chip for Ising Model With 512 Fully Connected Spins;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-12
5. Many-Qudit Representation for the Travelling Salesman Problem Optimisation;Journal of the Physical Society of Japan;2021-11-15
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