Hybrid MoCs for Long-Distance On-Chip Communications
Author:
Affiliation:
1. National Institute of Technology Karnataka,BRICS Laboratory,Department of Computer Science and Engineering,Mangalore,Bharat,575025
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9864330/9864331/09864553.pdf?arnumber=9864553
Reference13 articles.
1. A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms;abbas;The Journal of Supercomputing,2015
2. Hierarchical approach for hybrid wireless Network-on-chip in many-core era
3. HyWin: Hybrid Wireless NoC with Sandboxed Sub-Networks for CPU/GPU Architectures
4. Cycle-Accurate Network on Chip Simulation with Noxim
5. Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors
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1. Detection and Localization of Channel-Short Faults in Regular On-Chip Interconnection Networks;SN Computer Science;2023-08-30
2. Wireless Router Placements for Long-Distance Communications in MoCs;CSI Transactions on ICT;2023-08-23
3. Design of a Fault-Tolerant Pseudo-3D Routing;2023 IEEE International Test Conference India (ITC India);2023-07-23
4. Quantum Learning and Its Related Applications for the Future;Advances in Systems Analysis, Software Engineering, and High Performance Computing;2023-04-21
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