3D SoC integration, beyond 2.5D chiplets-Reference-Cited by-同舟云学术

3D SoC integration, beyond 2.5D chiplets

Published:2021-12-11 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Electron Devices Meeting (IEDM)
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Author:

Beyne Eric¹,Milojevic Dragomir¹,Van der Plas Geert¹,Beyer Gerald¹

Affiliation:

1. imec,Leuven,Belgium

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9720433/9720494/09720614.pdf?arnumber=9720614

Reference14 articles.

1. Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route

2. Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding

3. MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect;calvacante;DATE2021,0

4. The 3-D Interconnect Technology Landscape

5. Heterogeneous System Partitioning and the 3D Interconnect Technology Landscape;beyne;2020 Symposia on VLSI technology and Circuits Short course SC2–2,0

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