Author:
Jais Amish,Palsodkar Prasanna
Cited by
17 articles.
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1. High Speed 64 Bit Vedic & Booth Multiplier Implementation Using FPGA;2024 3rd International Conference on Artificial Intelligence For Internet of Things (AIIoT);2024-05-03
2. Design and Implementation of 32-bit Signed Divider for VLSI Applications;2023 7th International Conference on Electronics, Communication and Aerospace Technology (ICECA);2023-11-22
3. Design and Implementation of 3–bit Calculator for an ALU using Vertical and Crosswise Multiplication;2023 IEEE 13th International Conference on Control System, Computing and Engineering (ICCSCE);2023-08-25
4. A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2023-01-20
5. Modern Design and Testing of High Speed Vedic ALU Controller using Vedic Algorithms;Journal of The Institution of Engineers (India): Series B;2023-01-06