Defect classes-an overdue paradigm for CMOS IC testing-Reference-Cited by-同舟云学术

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Defect classes-an overdue paradigm for CMOS IC testing

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Container-title:Proceedings., International Test Conference
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Author:

Hawkins C.F.,Soden J.M.,Righter A.W.,Ferguson F.J.

Publisher

Int. Test Conference

Link

http://xplorestaging.ieee.org/ielx2/4035/11581/00527983.pdf?arnumber=527983

Cited by 85 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Cost Modeling for 2.5D and 3D Stacked ICs;Handbook of 3D Integration;2019-02-08

2. Clock-Less DFT-Less Test Strategy for Null Convention Logic;IEEE Transactions on Emerging Topics in Computing;2018-10-01

3. On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults;2015 IEEE 24th Asian Test Symposium (ATS);2015-11

4. Testing for gate oxide short defects using the detectability interval paradigm;it - Information Technology;2014-07-21

5. Hazard Initialized LOC Tests for TDF Undetectable CMOS Open Defects;2013 22nd Asian Test Symposium;2013-11

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