The physical design of on-chip interconnections-Reference-Cited by-同舟云学术

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The physical design of on-chip interconnections

Published:2003-03 Issue:3 Volume:22 Page:254-276
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:en
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Wisniewski M.Y.L.,Yashchin E.,Franch R.L.,Conrady D.P.,Maynard D.N.,Fiorenza G.,Noyan I.C.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/26533/01182071.pdf?arnumber=1182071

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A novel net-degree distribution model and its application to floorplanning benchmark generation;Integration;2007-07

2. Impact of interconnect length changes on effective materials properties (dielectric constant);Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07;2007

3. Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements;IBM Journal of Research and Development;2005-07

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