An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis

Author:

Chandan Karfa ,Sarkar D.,Mandal C.,Kumar P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 46 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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4. DEEQ: Data-driven End-to-End EQuivalence Checking of High-level Synthesis;2022 23rd International Symposium on Quality Electronic Design (ISQED);2022-04-06

5. A Hybrid Method for Equivalence Checking Between System Level and RTL;Journal of Circuits, Systems and Computers;2022-03-03

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