Process Variation-Aware Test for Resistive Bridges-Reference-Cited by-同舟云学术

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Process Variation-Aware Test for Resistive Bridges

Published:2009-08 Issue:8 Volume:28 Page:1269-1274
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Ingelsson U.,Al-Hashimi B.M.,Khursheed S.,Reddy S.M.,Harrod P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/5166543/05166639.pdf?arnumber=5166639

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Test Methodology for Defect-Based Bridge Faults;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-07

2. Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts;2021 IEEE 39th VLSI Test Symposium (VTS);2021-04-25

3. Test Methodology for Defect-based Bridge Faults;2020 IEEE International Test Conference in Asia (ITC-Asia);2020-09

4. Hardware Trojan Detection on a PCB Through Differential Power Monitoring;IEEE Transactions on Emerging Topics in Computing;2020

5. Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies;Journal of Electronic Testing;2019-02

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