A 23.5–32.5GHz, 17dBm P<sub>SAT</sub> and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology-Reference-Cited by-同舟云学术

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A 23.5–32.5GHz, 17dBm P_SAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology

Published:2023-07-03 Issue: Volume: Page:
ISSN:
Container-title:2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
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Author:

Passos Fábio¹,Lourenço Nuno¹,Mendes Luís¹,Martins Ricardo¹,Vaz João¹,Horta Nuno¹

Affiliation:

1. Instituto de Telecomunicações,Lisbon,Portugal

Funder

Instituto de Telecomunicações

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10192100/10192102/10192226.pdf?arnumber=10192226

Reference17 articles.

1. 24.6 An instantaneously broadband ultra-compact highly linear PA with compensated distributed-balun output network achieving >17.8 dBm P1 dB and >36.6% PAEP1 dB over 24 to 40 GHz and continuously supporting 64-/256-QAM 5G NR signals over 24 to 42 GHz;wang;ISSCC,2020

2. A 20.8-41.6-GHz Transformer-Based Wideband Power Amplifier with 20.4-dB Peak Gain Using 0.9-V 28-nm CMOS Process

3. A 28–34-GHz Stacked-FET Power Amplifier in 28-nm FD-SOI With Adaptive Back-Gate Control for Improving Linearity

4. A 24–30 GHz 31.7% Fractional Bandwidth Power Amplifier With an Adaptive Capacitance Linearizer

5. A 28GHz 41%-PAE linear CMOS power amplifier using a transformer-based AM-PM distortion-correction technique for 5G phased arrays

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