Author:
Matsumoto Naoyuki,Nakano Koji,Ito Yasuaki
Cited by
13 articles.
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1. An Energy Efficient Sorting Architecture with Cell-Gating for Top-K Sorting on FPGA;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06
2. k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-05
3. Resource Efficient Top-<i>K</i> Sorter on FPGA;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2022-09-01
4. A Novel Scheme for Real-Time Max/Min-Set-Selection Sorters on FPGA;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-07
5. Worst-Case O(N) Comparison-free Hardware Sorting Engine*;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021