Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards-Reference-Cited by-同舟云学术

Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards

Published:2022-09-12 Issue: Volume: Page:
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Container-title:2022 ACM/IEEE 4th Workshop on Machine Learning for CAD (MLCAD)
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Author:

Uhlmann Yannick¹,Essich Michael²,Bramlage Lennart²,Scheible Jurgen¹,Curio Cristobal²

Affiliation:

1. Reutlingen University,Electronics & Drives,Reutlingen,Germany

2. Reutlingen University,Cognitive Systems,Reutlingen,Germany

Funder

Ministry of Education

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9900062/9900076/09900083.pdf?arnumber=9900083

Reference34 articles.

1. Analog IC Design Using Precomputed Lookup Tables: Challenges and Solutions

2. Simple Baselines for Human Pose Estimation and Tracking;xiao;Technical Report,2018

3. GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning

4. Machine Learning Based Procedural Circuit Sizing and DC Operating Point Prediction;uhlmann;SMACD / PRIME 2021 International Conference on SMACD and 16th Conference on PRIME dummydata,2021

5. Deep Reinforcement Learning for Analog Circuit Sizing

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