Hardware Encryption logic on FPGA and Power Consumption
Author:
Affiliation:
1. Aleksander Moisiu University,Faculty of Information Technology,Durres,Albania
2. Technical University of Sofia,Faculty of Telecommunications,Sofia,Bulgaria
Funder
Bulgarian National Science Fund
CEEPUS
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9854388/9854389/09854482.pdf?arnumber=9854482
Reference15 articles.
1. A MUX based Latch Technique for the detection of HardwareTrojan using Path Delay Analysis
2. The MUX-Based PUF Architecture for Hardware Security
3. A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits
4. Developing Attack Resilience in Y86 Processor using Logic Locking;r e;2021 IEEE 12th Annual Information Technology Electronics and Mobile Communication Conference (IEMCON),2021
5. On SAT-Based Attacks On Encrypted Sequential Logic Circuits
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