VLSI implementation of a high speed single precision floating point unit using verilog-Reference-Cited by-同舟云学术

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VLSI implementation of a high speed single precision floating point unit using verilog

Published:2013-04 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES
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Author:

Ushasree G.,Dhanabal R,Kumar sahoo Sarat

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6550118/6558050/06558204.pdf?arnumber=6558204

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A High Performance and Full Utilization Hardware Implementation of Floating Point Arithmetic Units;2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS);2021-11-28

2. Implementation of Low Power and Area Efficient Floating-Point Fused Multiply-Add Unit;Proceedings of the International Conference on Soft Computing Systems;2015-12-29

3. Design of Reversible Logic Based ALU;Proceedings of the International Conference on Soft Computing Systems;2015-12-29

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