A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs

Author:

Jain Abhishek Kumar,Omidian Hossein,Fraisse Henri,Benipal Mansimran,Liu Lisa,Gaitonde Dinesh

Publisher

IEEE

Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Simopt - Simulation Pass for Speculative Optimisation of FPGA-CAD Flow;2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS);2024-07-29

2. HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory;2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2024-05-05

3. GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network;Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2024-04

4. HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAs;Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2024-04

5. Open-Source SpMV Multiplication Hardware Accelerator for FPGA-Based HPC Systems;Lecture Notes in Computer Science;2024

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