Lead-Free BiSnAg Soldering Process for Voidless Semiconductor Packaging-Reference-Cited by-同舟云学术

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Lead-Free BiSnAg Soldering Process for Voidless Semiconductor Packaging

Published:2023-08 Issue:8 Volume:13 Page:1310-1315
ISSN:2156-3950
Container-title:IEEE Transactions on Components, Packaging and Manufacturing Technology
language:
Short-container-title:IEEE Trans. Compon., Packag. Manufact. Technol.

Author:

Yeo Siang Miang¹^ORCID,Yow Ho-Kwang²^ORCID,Yeoh Keat Hoe²^ORCID

Affiliation:

1. Amkor Technology Incorporation, Selangor, Malaysia

2. Department of Electrical and Electronics Engineering, Lee Kong Chian Faculty of Engineering and Science, and the Center for Photonics and Advanced Material Research, Universiti Tunku Abdul Rahman, Selangor, Malaysia

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/5503870/10255328/10202234.pdf?arnumber=10202234

Reference25 articles.

1. Trends of power electronic packaging and modeling;liu;Proc 10th Electron Packag Technol Conf,2009

2. Failure modes and FEM analysis of power electronic packaging

3. Study on solder void for PiP large solder area ultrathin die in solder reflow

4. Semiconductor Power Devices

5. Power electronics technology at the dawn millenium-status and future;vanwyk;IEEE Proc Power Electron Spec Conf (PESC),1999

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