Layout Optimization of Integrated Inductors and Capacitors Using TGV Technology-Reference-Cited by-同舟云学术

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Layout Optimization of Integrated Inductors and Capacitors Using TGV Technology

Published:2024 Issue: Volume: Page:1-1
ISSN:2156-3950
Container-title:IEEE Transactions on Components, Packaging and Manufacturing Technology
language:
Short-container-title:IEEE Trans. Compon., Packag. Manufact. Technol.

Author:

Li Wenlei¹^ORCID,Zhang Jihua¹^ORCID,Wang Lingyue¹^ORCID,Gao Libin¹,Chen Hongwei¹,Fang Zhen¹,Cai Xingzhou²,Li Yong²

Affiliation:

1. School of Integrated Circuit Science and Engineering, State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China

2. 3D Chips (Guangdong) Technology Co. Ltd, Dongguan, China

Funder

Fundamental Research Funds for the Central Universities

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/5503870/5673025/10374140.pdf?arnumber=10374140

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