Improve Chip Side Wall Crack Issue in Nanometer Packing Process of Semiconductor-Reference-Cited by-同舟云学术

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Improve Chip Side Wall Crack Issue in Nanometer Packing Process of Semiconductor

Published:2021-02 Issue:2 Volume:11 Page:173-180
ISSN:2156-3950
Container-title:IEEE Transactions on Components, Packaging and Manufacturing Technology
language:
Short-container-title:IEEE Trans. Compon., Packag. Manufact. Technol.

Author:

Wang Chia-Nan¹,Hsueh Ming-Hsien¹^ORCID,Lai Chao-Jung¹,Chung Chih-Chao²,Chen Wen-Chung³,Wang Shi-Hao¹

Affiliation:

1. National Kaoshiung University of Science and Technology, Kaohsiung City, Taiwan

2. General Research Service Center, National Pingtung University Science and Technology, Pingtung, Taiwan

3. Advanced Semiconductor Engineering Inc., Kaohsiung City, Taiwan

Funder

Ministry of Science and Technology

National Kaoshiung University of Science and Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/5503870/9355428/09279332.pdf?arnumber=9279332

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Supporting Luxury Hotel Recovered in Times of COVID-19 by Applying TRIZ Method: A Case Study in Taiwan;Systems;2022-03-08

2. Novel Design of a Modular Multi-stage Crusher with Adaptive Clearance by TRIZ Method;Advances in Mechanical Design;2022

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