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New Multiport I/O Model for Power-Aware Signal Integrity Analysis

  • Published:2016-03 Issue:3 Volume:6 Page:447-454
  • ISSN:2156-3950
  • Container-title:IEEE Transactions on Components, Packaging and Manufacturing Technology
  • language:
  • Short-container-title:IEEE Trans. Compon., Packag. Manufact. Technol.

Author:

Dghais Wael,Rodriguez Jonathan

Funder

Fundação para a Ciência e Tecnologia

ENIAC Joint Undertaking (THIN but Great Silicon 2 Design Objects–GA)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Electronic, Optical and Magnetic Materials

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A New Method for Power-Aware Signal Integrity Analysis with Spice Model of Power Distribution Network;2022 IEEE 22nd International Conference on Communication Technology (ICCT);2022-11-11

2. Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners;Sensors;2022-08-30

3. Pre-driver Modeling and Jitter Estimation under Power Supply Noise;2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS);2021-10-17

4. Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations;Sensors;2021-09-10

5. Behavioral Modeling of Tunable I/O Drivers With Preemphasis Including Power Supply Noise;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-01
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