Signal Integrity Analysis of Through-Silicon Via (TSV) With a Silicon Dioxide Well to Reduce Leakage Current for High-Bandwidth Memory Interface-Reference-Cited by-同舟云学术

Signal Integrity Analysis of Through-Silicon Via (TSV) With a Silicon Dioxide Well to Reduce Leakage Current for High-Bandwidth Memory Interface

Published:2023-05 Issue:5 Volume:13 Page:700-714
ISSN:2156-3950
Container-title:IEEE Transactions on Components, Packaging and Manufacturing Technology
language:
Short-container-title:IEEE Trans. Compon., Packag. Manufact. Technol.

Author:

Kim Hyunwoong¹^ORCID,Lee Seonghi¹^ORCID,Park Jongcheol²^ORCID,Shin Yujun³^ORCID,Woo Seongho¹,Kim Jongwook⁴,Cho Jaeyong⁵^ORCID,Ahn Seungyoung¹^ORCID

Affiliation:

1. Cho Chun Shik Graduate School of Mobility, Korea Advanced Institute of Science and Technology, Daejeon, South Korea

2. National NanoFab Convergence Technology, National NanoFab Center, Daejeon, South Korea

3. Keimyung University, Daegu, South Korea

4. SK Hynix, Icheon, South Korea

5. Huwin, Seongnam, South Korea

Funder

National Research Foundation of Korea

Institute of Information & communications Technology Planning & Evaluation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Electronic, Optical and Magnetic Materials

Link

Reference30 articles.

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design Methodology of Through-Silicon via for Crosstalk Optimization Based on Impedance;2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa);2024-05-20

3. Reliability Concerns of TSV-Based 3-D Integration: Impact of Interfacial Crack;IEEE Transactions on Components, Packaging and Manufacturing Technology;2023-11