Hardware-efficient fair queueing architectures for high-speed networks
Author:
Publisher
IEEE Comput. Soc. Press
Link
http://xplorestaging.ieee.org/ielx2/3539/10629/00493359.pdf?arnumber=493359
Cited by 31 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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2. Aggregate Flow-Based Performance Fairness in CMPs;ACM Transactions on Architecture and Code Optimization;2016-12-28
3. Hardware implementation study of several new egress link scheduling algorithms;Journal of Parallel and Distributed Computing;2012-08
4. Fully hardware based WFQ architecture for high-speed QoS packet scheduling;Integration;2012-01
5. Principles of Fairness Quantification in Queueing Systems;Network Performance Engineering;2011
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