Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction-Reference-Cited by-同舟云学术

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Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction

Published:2022-10 Issue: Volume: Page:
ISSN:
Container-title:2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)
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Author:

Bera Rahul¹,Kanellopoulos Konstantinos¹,Balachandran Shankar²,Novo David³,Olgun Ataberk¹,Sadrosadat Mohammad¹,Mutlu Onur¹

Affiliation:

1. ETH Zürich

2. Intel Processor Architecture Research Lab

3. LIRMM, Univ. Montpellier, CNRS

Funder

Semiconductor Research Corporation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9923754/9923780/09923900.pdf?arnumber=9923900

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2. A Generalized Residue Number System Design Approach for Ultralow-Power Arithmetic Circuits Based on Deterministic Bit-Streams;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

3. IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

4. Decoupled Vector Runahead;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

5. CLIP: Load Criticality based Data Prefetching for Bandwidth-constrained Many-core Systems;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

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