Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction-Reference-Cited by-同舟云学术

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Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction

Published:2022-10 Issue: Volume: Page:
ISSN:
Container-title:2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)
language:
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Author:

Bera Rahul¹,Kanellopoulos Konstantinos¹,Balachandran Shankar²,Novo David³,Olgun Ataberk¹,Sadrosadat Mohammad¹,Mutlu Onur¹

Affiliation:

1. ETH Zürich

2. Intel Processor Architecture Research Lab

3. LIRMM, Univ. Montpellier, CNRS

Funder

Semiconductor Research Corporation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9923754/9923780/09923900.pdf?arnumber=9923900

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2. Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

3. Compiler-Directed Whole-System Persistence;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

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5. Efficient cache replacement framework based on access hotness for spacecraft processors;CHIN SPACE SCI TECHN;2024

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