Design of Various Modulation Schemes using DDS

Author:

Jothimani S.1,Narmadha A.1,Santhiya C.1,Priya S.SHANMUGA1

Affiliation:

1. Electronics and Communication Engineering M.Kumarasamy College of Engineering,Karur,India

Publisher

IEEE

Reference17 articles.

1. Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

2. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

3. A2.2 GHz sub-samplingPLLwith 0.16psrms jitter and -125dBc/Hz in-band phase noise at 700µW loop-components power;gao;Proc IEEE VLSI Circuits Symp,2010

4. A Type-I Sub-Sampling PLL With a $100\times100\,\,\mu\text{m}^{2}$ Footprint and −255-dB FOM

5. Estimating SecuritiesExchange Utilizing Profound Neural Networks;jothimani;International Journal of Grid and Distributed Computing,2019

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2. Design and FPGA Implementation of Satellite Telemetry Transmitter Employing PCM/PSK/PM Sub-Carrier Modulation Using DDS;2024 International Conference on Electronics, Computing, Communication and Control Technology (ICECCC);2024-05-02

3. Frequency Calibration System for wBMS;2023 International Conference on Electrical, Electronics, Communication and Computers (ELEXCOM);2023-08-26

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