VLSI Design of Majority Logic based Wallace Tree Multiplier-Reference-Cited by-同舟云学术

VLSI Design of Majority Logic based Wallace Tree Multiplier

Published:2023-02-23 Issue: Volume: Page:
ISSN:
Container-title:2023 7th International Conference on Computing Methodologies and Communication (ICCMC)
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Author:

S Jothimani¹,M Mugunthan¹,Kumar M Kishore¹,Krithik Roshan S Harish¹

Affiliation:

1. M.Kumarasamy College of Engineering,Dept. of Electronics and Communication Engineering,Karur,TamilNadu,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10083318/10083503/10083704.pdf?arnumber=10083704

Reference16 articles.

1. Investigation on Variable Latency Speculative Approach in Parallel Prefix Adders;kaarthik;International Journal of Future Generation Communication and Networking,2020

2. Performance Investigation on VLSI Adders to Reduce Power and Delay;kaarthik;International Journal of Grid and Distributed,2020

3. Variable Latency approach in VLSI adder Implemented to Reduce Area and Power

4. AN EFFICIENT FPGA IMPLEMENTATION OF THE CLOCK GATED RSFQ MATRIX MULTIPLIER;kaarthik;Turkish Journal of Physiotherapy and Rehabilitation,2021

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1. A Comparative Analysis of Switched Gate Implementations in Wallace Tree Multipliers;2024 3rd International Conference on Artificial Intelligence For Internet of Things (AIIoT);2024-05-03

2. A Serial-Parallel-Based 4-Bit Novel Multiplier: Design, Implementation, and Performance Analysis;2023 IEEE Silchar Subsection Conference (SILCON);2023-11-03

3. High Performance, Low Power Wallace Tree Multiplier;International Journal of Recent Technology and Engineering (IJRTE);2023-07-30