Author:
Baraza J.C.,Gracia J.,Gil D.,Gil P.J.
Cited by
23 articles.
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1. SEU/SET Evaluation of Digital VLSI Design from Register Transfer Level to Layout Level;2023 7th International Conference on Electrical, Mechanical and Computer Engineering (ICEMCE);2023-10-20
2. Large-Scale Application of Fault Injection into PyTorch Models -an Extension to PyTorchFI for Validation Efficiency;2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S);2023-06
3. MetaFS: Model-driven Fault Simulation Framework;2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2022-10-19
4. Machine Learning Approach for Accelerating Simulation-based Fault Injection;2021 IEEE Nordic Circuits and Systems Conference (NorCAS);2021-10-26
5. Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models;2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2021-10-06