An approach to functional testing of VLIW architectures-Reference-Cited by-同舟云学术

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An approach to functional testing of VLIW architectures

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Container-title:Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)
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Author:

Beardo M.,Bruschi F.,Ferrandi F.,Sciuto D.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/7154/19255/00889555.pdf?arnumber=889555

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Facilitating the Bootstrapping of a New ISA;Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems;2023-06-13

2. On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2014-04

3. On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors;VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design;2013

4. Generation of test data for verification of caching mechanisms and address translation in microprocessors;Programming and Computer Software;2010-01

5. An implementation for test-time reduction in VLIW transport-triggered architectures;Journal of Electronic Testing;2002

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