Author:
Barbagallo S.,Lobetti Bodoni M.,Medina D.,Corno F.,Prinetto P.,Sonza Reorda M.
Cited by
7 articles.
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1. Scan and Automated Test Pattern Generation in VLSI;2024 5th International Conference on Image Processing and Capsule Networks (ICIPCN);2024-07-03
2. Routing-aware scan chain ordering;ACM Transactions on Design Automation of Electronic Systems;2005-07
3. Layout-aware scan chain synthesis for improved path delay fault coverage;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2005-07
4. Layout driven synthesis of multiple scan chains;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2003-03
5. Reducing the cost of scan in deep sub-micron designs;Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)