A Study of an Infrastructure for Research and Development of Many-Core Processors
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5372726/5372727/05372768.pdf?arnumber=5372768
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment;IEICE Transactions on Information and Systems;2018
2. Effective Parallel Simulation of ArchHDL under Manycore Environment;2015 Third International Symposium on Computing and Networking (CANDAR);2015-12
3. ArchHDL: A Novel Hardware RTL Design Environment in C++;Lecture Notes in Computer Science;2015
4. Modeling and Simulation of a Many-core Architecture Using SystemC;Procedia Technology;2014
5. An FPGA-based scalable simulation accelerator for tile architectures;ACM SIGARCH Computer Architecture News;2011-12-19
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